Traditionally CMOS A/D converters have been designed by using switched-capacitor technique. But these kind of A/D converters usually call for linear capacitors. In a digital CMOS process, there is only one poly layer available. To create linear capacitors in the digital CMOS process, extra process steps are needed, which would increase the cost. It is therefore of interest to design CMOS A/D converters in the digital CMOS process. This can be accomplished by using the current mode approach, see for example: "Analog IC Design: the Current-Mode Approach", C. Toumazou, F. J. Lidgey and D. G. Haig (Eds), Peter Peregrinus Ltd., 1990 and "Switched-Currents: an Analogue Technique for Digital Technology", C. Toumazou, J. B. Hughes and N. C Bettersby (Eds), Peter Peregrinus Ltd., 1993.
A high-speed pipelined A/D converter was presented in "A CMOS transistor--only 8-b 4.5--Ms/s pipelined analog-to-digital converter using fully-differential current-mode curcuit techniques" C. -Y. Wu, C. -C. Chen and J. -J. Cho, IEEE J. Solid--State Circuits, May 1995 pp. 522-532. In FIG. 1 there is shown a 1-bit-per-stage architecture. The A/D converter consists of a current sample-and-hold (S/H) circuit 1 at the input and 8 identical 1-bit pipelined stages 2. Each stage 2 contains a current S/H 3 circuit, an inter stage current amplifier/adder 4, a current comparator 5 and current references 6.
If the input current I.sub.j is positive, the output of the current comparator is ONE and the residual current to the next stage is (2I.sub.j -I.sub.ref). If the input current I.sub.j is negative, the output of the current comparator is ZERO and the residual current to the next stage is (2I.sub.j +I.sub.ref). The residual current I.sub.j+l is then sent to the next stage to determine next bit. The sampled input currents can therefore be pipelined to determine its digital codes sequentially.
In practical realization the function of multiplication by 2 can be realized in the S/H circuit by using a current mirror as in the reference "A CMOS transistor--only 8-b 4.5--Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques". However, the current mirrors include extra capacitive load to the S/H circuit, which limits the speed. Another drawback is that every stage is treated equally and therefore the power consumtion cannot be optimized.
In U.S. Pat. No. 4,894,657: "Pipelined analog-to-digital architecture with parallel-autozero analog signal processing" the invention relates to an A/D converter for converting analog signals to digital signals and in particular to a pipelined A/D converter having a cascade connection of A/D-D/A sub-blocks respectively for determining partial bits of a conversion output. The cited invention is based on the traditional voltage-mode approach, and therefore is not in the scope of the invention where a current mode approach is used.